1. Field of the Invention
This invention relates to integrated circuit structures. More particularly, this invention relates to a multilevel gate array type integrated circuit structure comprising a first plurality of integrated circuit structures constructed at one level on a substrate and a second plurality of integrated circuit structures constructed at a second level above the first level with access, perpendicular to the plane of the substrate, provided to all regions of all of the integrated circuit structures, regardless of the level at which the integrated circuit structures are located.
2. Description of the Related Art
In the formation of integrated circuit structures such as, for example, MOS devices, a particular type of construction known as a gate array construction is sometimes carried out wherein an array of active devices is constructed on a substrate, such as a semiconductor wafer, and then covered with a layer of oxide, without however, forming the metal bus wiring layers over the structure to thereby form specific structures or circuits, e.g., an invertor, a ring oscillator, NAND gates, and other basic circuits. In this type of construction the source, drain, and gate regions are formed in/on the semiconductor wafer, including polysilicon electrodes, silicide contacts, etc., over the active device regions, followed by formation of an oxide layer. Contact openings are not cut through the oxide to the underlying source and drain regions, or gate electrode contact regions or to electrode portions, however, at this point.
The gate array structure, finished to the point just described, may then be stored or inventoried for future use in the construction of a particular circuitry thereon, in which case, contact openings will be formed to the particular underlying active devices to be incorporated into the particular circuitry and appropriate metal lines and vias will then be formed to complete the wiring of the desired circuitry.
Such a gate array construction technique has proved to be a valuable tool in the formation of custom circuitry, wherein a generic gate array structure may be rapidly converted to a particular wiring structure without the need to carry out all of the construction steps normally needed to construct an entire integrated circuit structure on a bare (unprocessed) semiconductor wafer. This has the commercial advantage of minimizing the time it takes for a prototype design to reach the marketplace. However, in order for such a construction technique to function properly, there must be unrestricted access to all of the regions of all of the active devices in the gate array structure. That is, for an MOS type gate array structure, for example, it must be possible, after the construction of the gate array structure, to still have access, through contact openings directly formed through the overlying insulation normal to the plane of the substrate, to all of the underlying source and drain regions, and gate electrode contact regions comprising the MOS structures.
It is also known to construct active devices of integrated circuit structures stacked above one another to conserve lateral space on the underlying substrate. However, this type of construction is limited to use in the construction of dedicated integrated circuit structures, i.e., integrated circuit structures wherein the particular circuitry has been predetermined prior to construction of the structure. Indeed, in at least some such constructions, some of the inter-electrode wiring or interconnections are already incorporated into the underlying layers before construction thereover of further active integrated circuit devices. Typical stacked structures of this type are shown in Kugimiya et al. U.S. Pat. No. 4,487,635; Sakurai U.S. Pat. No. 4,489,478; Chatterjee U.S. Pat. No.4,554,572; Sasaki et al. U.S. Pat. No. 4,630,089; Szluk et al. U.S. Pat. No. 4,679,299; and Sugahara et at. U.S. Pat. No. 5,006,913.
Each of these types of construction has its own advantages. The stacked type of construction conserves lateral space, thus permitting increases in the density of the active devices formed on a substrate without the complications which arise each time a new scaling down of the size of the active devices is undertaken. On the other hand, the flexibility and rapid construction of custom circuitry which is made possible by the use of gate array type of construction undeniably results in certain advantages.
It would, therefore, be highly desirable if the features and advantages of both types of construction could be incorporated into a single integrated circuit structure construction.